The NEORV32 RISC-V Processor

What's Changed

• [rtl] cleanup main package file by @stnolting in https://github.com/stnolting/neorv32/pull/447
• [sw] rework intrinsic libraries by @stnolting in https://github.com/stnolting/neorv32/pull/448
• ✨ Add CFU R4-type instructions by @stnolting in https://github.com/stnolting/neorv32/pull/449
• 🐛 [rtl] core trap fixes by @stnolting in https://github.com/stnolting/neorv32/pull/450
• [sw] Remove B ISA extension intrinsic library by @stnolting in https://github.com/stnolting/neorv32/pull/451
• ✨ [CFU] add support for custom R5-type instructions by @stnolting in https://github.com/stnolting/neorv32/pull/452
• [rtl] instruction prefetch buffer (IPB) improvements by @stnolting in https://github.com/stnolting/neorv32/pull/455
• 🧪 [OCD] optimize firmware (park-loop) by @stnolting in https://github.com/stnolting/neorv32/pull/456
• 🐛 [rtl] fix iCache block error bug by @stnolting in https://github.com/stnolting/neorv32/pull/457
• 🐛 [rtl] fix MEPC value for instruction access faults by @stnolting in https://github.com/stnolting/neorv32/pull/458
• [rtl] mtval CSR is now r/w by @stnolting in https://github.com/stnolting/neorv32/pull/460
• [rt] SoC: rework r/w access logic and reset by @stnolting in https://github.com/stnolting/neorv32/pull/461
• [rtl] CPU: optimizations and cleanup by @stnolting in https://github.com/stnolting/neorv32/pull/462

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.7.8...v1.7.9