The NEORV32 RISC-V Processor

What's Changed

• CPU RTL optimization by @stnolting in https://github.com/stnolting/neorv32/pull/857
• :warning: remove WDT + TRNG interrupts; :bug: fix bug in core-complex clocking during sleep by @stnolting in https://github.com/stnolting/neorv32/pull/858
• :warning: rework ONEWIRE and GPTMR interrupts by @stnolting in https://github.com/stnolting/neorv32/pull/859
• :warning: rework TWI interrupt by @stnolting in https://github.com/stnolting/neorv32/pull/860
• :bug: fix DMA fence flag, :warning: rework CPU FIRQs by @stnolting in https://github.com/stnolting/neorv32/pull/864
• Support tool-specific standard flags in makefile by @jpf91 in https://github.com/stnolting/neorv32/pull/862
• :warning: rework TWI module by @stnolting in https://github.com/stnolting/neorv32/pull/865
• add back TWI clock stretching option by @stnolting in https://github.com/stnolting/neorv32/pull/867
• [SLINK] split interrupt into two FIRQs by @stnolting in https://github.com/stnolting/neorv32/pull/868
• B ISA extensions only contains Zba + Zbb + Zbs by @stnolting in https://github.com/stnolting/neorv32/pull/869
• add additional SPI and SDI interrupt conditions by @stnolting in https://github.com/stnolting/neorv32/pull/870

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.9.7...v1.9.8