Development of a Universal FPGA-Based Coprocessor for 5G NR and WLAN LDPC Coding

Low-density parity-check (LDPC) codes are widely used in modern communication systems due to their near-capacity error correction performance. This paper presents a practical FPGA implementation of a universal hardware coprocessor for LDPC encoding and decoding, focusing on a system-level architecture, achievable data rate, latency measurements, and hardware resource utilization. The LDPC coding is realized by the Xilinx hardware macros available in the Xilinx RF-SoC FPGAs. We explore various design simplifications, including core combining, memory management, and data scheduling, to achieve high throughput while maintaining the lowest implementation

complexity. The proposed architecture is implemented on an FPGA platform and is equipped with 10 Gb/s Ethernet interfaces, demonstrating real-time decoding capabilities and improved performance compared to software-based approaches. Experimental results validate the design, showcasing its applicability in high-speed communication systems. This work can serve as a reference for engineers and researchers aiming to deploy LDPC decoding in FPGA-based environments by reusing the

existing Intellectual Property (IP), which is freely available in Xilinx SoC.