Published May 30, 2023 | Version CC BY-NC-ND 4.0
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Design and Implementation of High Speed Low Power Decimation Filter for Hearing AID Applications

Creators

  • 1. Department of Electronics and Communication Engineering, Sri Vasavi Engineering College, Pedatadepalli (A.P), India.
  • 2. Department of Electronic and Communication, Sri Vasavi Engineering College, Tadepalligudem, Pedatadepalli (A.P), India.

Contributors

Contact person:

  • 1. Department of Electronic and Communication, Sri Vasavi Engineering College, Tadepalligudem, Pedatadepalli (A.P), India.

Description

Abstract: This work is focused on designing and implementing a decimation filter specifically intended for use in hearing aid applications. The filter utilizes distributed arithmetic (DA) and is described in this brief. Our proposal involves the development of a reconfigurable finite impulse response (FIR) filter, which utilizes both offset binary code (OBC) and binary distributed arithmetic (DA) techniques. Additionally, we utilize canonic signed digit (CSD) representation to develop decimation filters, which include the CIC filter, half band filter, and corrector filter. In this work, we have implemented a decimation filter using Matlab Simulink. We have utilized Xilinx Vivado 19.2 to execute the FIR filters, binary DA filters, and OBC DA-based filters. Our focus is on implementing these filters using VLSI architecture, in order to achieve low power consumption, reduced latency, less area, and fast speed.

Notes

Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP) © Copyright: All rights reserved.

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Journal article: 2277-3878 (ISSN)

References

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Subjects

ISSN: 2277-3878 (Online)
https://portal.issn.org/resource/ISSN/2277-3878#
Retrieval Number: 100.1/ijrte.A75640512123
https://www.ijrte.org/portfolio-item/A75640512123/
Journal Website: www.ijrte.org
https://www.ijrte.org
Publisher: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP)
https://www.blueeyesintelligence.org