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Journal article Open Access

Design and Implementation of High Speed Low Power Decimation Filter for Hearing AID Applications

Dr. S V V Satyanarayana; K Teja Sri; K Madhavi; G Jhansi; B Jaya Sri

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K Teja Sri

Abstract: This work is focused on designing and implementing a decimation filter specifically intended for use in hearing aid applications. The filter utilizes distributed arithmetic (DA) and is described in this brief. Our proposal involves the development of a reconfigurable finite impulse response (FIR) filter, which utilizes both offset binary code (OBC) and binary distributed arithmetic (DA) techniques. Additionally, we utilize canonic signed digit (CSD) representation to develop decimation filters, which include the CIC filter, half band filter, and corrector filter. In this work, we have implemented a decimation filter using Matlab Simulink. We have utilized Xilinx Vivado 19.2 to execute the FIR filters, binary DA filters, and OBC DA-based filters. Our focus is on implementing these filters using VLSI architecture, in order to achieve low power consumption, reduced latency, less area, and fast speed.

Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP) © Copyright: All rights reserved.
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  • Niveditha, V.R., Palaniappan, S., Naresh, K., Nayak, C.K. and Swapna, B. "High speed low area decimation filter for hearing aid application". International Journal of Speech Technology, 25(3), 2022, pp.633-639.

  • Chitra, E., Vigneswaran, T. and Malarvizhi, S. "Analysis and implementation of high performance reconfigurable finite impulse response filter using distributed arithmetic". Wireless Personal Communications, 102, 2018, pp.3413-3425.

  • SATTI, V.S. and Sriadibhatla, S. "Hybrid self-controlled precharge-free CAM design for low power and high performance". Turkish Journal of Electrical Engineering and Computer Sciences, 27(2), 2019, pp.1132-1146

  • Satyanarayana, S.V.V., Shailendra, S.R., Ramakrishnan, V.N. and Sriadibhatla, S. "Dual-chirality GAA-CNTFET-based SCPF-TCAM cell design for low power and high performance. Journal of Computational Electronics", 18, 2019, pp.1045-1054.

  • Awasthi, V. and Raj, K. "Application of hardware efficient CIC compensation filter in narrow band filtering. World Academy of Science", Engineering and Technology International Journal of Electronics and Communication Engineering, 8(9), 2014.

  • Mohanty, B.K. and Meher, P.K. "A high-performance energy-efficient architecture for FIR adaptive filter based on new distributed arithmetic formulation of block LMS algorithm". IEEE transactions on signal processing, 61(4), 2012, pp.921-932.

  • Raghuvanshi, S. and Goyal, S. "Development of digital signal processing platform for digital hearing aid". Int. J. Adv. Res. Electrical Electronics Instrumentation Eng (An ISO 3297: 2007 Certified Organization), 3(2), 2014.

  • Awasthi, V. and Raj, K. "A New Approach to Design an Efficient CIC Decimator Using Signed Digit Arithmetic". International Journal of Electronics and Communication Engineering, 7(11), 2014, pp.1477-1486.

  • Ghamkhari, S.F. and Ghaznavi-Ghoushchi, M.B. May. "A low-power low-area architecture design for distributed arithmetic (DA) unit". In 20th Iranian Conference on Electrical Engineering (ICEE2012), 2012 (pp. 232-237). IEEE.

  • Sohel, M.A., Reddy, K.C.K. and Sattar, S.A. " Design of low power sigma delta ADC". International Journal of VLSI Design & Communication Systems, 3(4), 2012, p.67.

  • Pandu, S. "Design and VLSI implementation of a decimation filter for hearing Aid applications." (Doctoral dissertation,), 2007.

  • Venugopal, V., Abed, K.H. and Nerurkar, S.B., 2005, April. Design and implementation of a decimation filter for hearing aid applications. In Proceedings. IEEE Southeast Con, 2005. (pp. 111-115). IEEE.

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