OpenASIP 2.0: Co-Design Toolset for RISC-V Application-Specific Instruction-Set Processors

Application-specific instruction-set processors (ASIPs) are interesting for improving performance or energy-
efficiency for a set of applications of interest while supporting flexibility via compiler-supported programmability. In the
past years, the open source hardware community has become extremely active, mainly fueled by the massive popularity of the open-standard RISC-V instruction set architecture. However, the community still lacks an open source ASIP co-design tool that supports rapid customization of RISC-V-based processors with an automatically retargetable programming toolchain. To this end, we introduce OpenASIP 2.0: A co-design toolset that is built on top of our earlier ASIP customization toolset work by extending it to support customization of RISC-V- based processors. It enables RTL generation as well as high-level language programming of RISC-V processors with custom instructions. In this paper, in addition to describing the toolset’s key technical internals, we demonstrate it with customization cases for AES, CRC and SHA applications. With the example custom instructions easily integrated using the toolset, the run time was reduced by 44% on average compared to the standard RISC-V ISA. The speedups were achieved with a negligible
datapath area overhead of 1.5%, and a 1.4% reduction in the maximum clock frequency.

A pre-print accepted to ASAP 2022 https://www.asap2022.org/.