De-RISC: Dependable Real-time RISC-V Infrastructure for Safety-critical Space and Avionics Computer Systems

The world market for aviation and space computing systems faces a significant shift caused by the loss of momentum of the traditionally used PowerPC and SPARC instruction set architectures in the commercial domain. This means that the space industry is not able to leverage training, software tools, etc. from the commercial domain and this fuels a need to shift to architectures present in larger commercial markets.

The De-RISC project brings together leading European entities within the areas of fault-tolerant microprocessors, hypervisors, embedded safety-critical software and mixed-criticality systems in an effort to commercialize a complete technology stack consisting of an FPGA space grade development board, system-on-chip design and software stack. The goal is to create a platform for the
aerospace industries implementing the open RISC-V microprocessor instruction set architecture together with specific features to address the needs of the target industries and to adopt modern commercial technology to allow leveraging technology development from other domains.