Cost Optimization at Early Stages of Design Using Deep Reinforcement Learning (DRL)

There has unarguably been an increase in how complex modern systems are when it comes to Chips (SoCs). This, coupled with the rising demand for a time-to-market provision lower than usual, automation assumes an ultimately essential component in designing hardware. As a matter of particular relevance, this comes in handy for tasks that are time-consuming or overly complex in nature. By optimizing the cost of design for any hardware component, automation becomes an effective reality. In fact, design cost can be reliant on a number of objectives, in semblance to the trade-off between the hardware and the software. Because this task can often be multiplexed, the designer in charge will have little to no means of delivering timely and efficient optimization for the even larger and more compound models. This paper initially demonstrates that the DRL is an ideal solution for the problem encountered in this process. Thereafter, using a Pointer Network, which is a system of neural elements painstakingly tailored to play a role in the application of combinatorial complexities, we measure a trio of DRL algorithms against a specified challenge. The outcomes realized in the many cases showcased the developments that have occurred by the said DRL algorithms in comparison to traditional models for optimization. Furthermore, through the use of reward re-dispensation suggested in the recently published RUDDER technique, the paper garners substantial betterments on the part of complex designs. Herein, the average optimization obtained is 15.18 percent area-wise. On the application size, the average is 8.25 percent, while being 8.12 percent on the executive time. This happens with industrial hardware-cum-software interface design data sets.