Multi-level storage in phase-change memory devices

Phase-change memory (PCM) is a promising technology for both storage class memory and emerging nonvon
Neumann computing systems. For both applications, a key enabling technology is the ability to store
multiple resistance levels in a single device. Multi-level storage is achieved by modulating the size of the
crystalline/amorphous phase configuration. A key challenge, in this respect, is the device variability, which
can be addressed by iterative programming schemes. When retrieving the stored information, the two
additional challenges are resistance drift and low-frequency noise. Resistance drift is attributed to a
spontaneous structural relaxation of the unstable amorphous states to a more stable “ideal glass” state and is
well captured by a collective relaxation model. This model, in conjunction with the electrical transport
models, provides a complete description of the time/temperature dependence of electrical transport in PCM
devices. To counter resistance drift, several strategies have been devised, such as drift-resilient read-out
mechanisms as well as coding and detection schemes. These techniques have helped to demonstrate storing
up to 8 levels of information in a single PCM device. Yet another fascinating new approach is that of driftresilient
device architectures. Experimental results on prototype devices show remarkable promise in terms
of eliminating drift as well as low-frequency noise.