The Digital Autonomy with RISC-V in Europe, Special Grant Agreement 1 (DARE SGA1) project is the first phase of a groundbreaking initiative to strengthen Europe’s technological sovereignty in High-Performance Computing (HPC) and Artificial Intelligence (AI). Supported by the EuroHPC Joint Undertaking, and coordinated by the Barcelona Supercomputing Center (BSC-CNS), DARE SGA1 unites 38 leading partners, and seven affiliated entities, from across Europe to develop next-generation European processors and computing systems, including an optimized software ecosystem, designed for research and industry applications.
Key Technological Innovations
At the heart of the DARE SGA1 project is the development of three RISC-V-based chiplets, each serving a critical function in HPC and AI computing:
- Vector accelerator (VEC) for high-precision HPC and emerging applications in the HPC-AI convergence domain
- AI Processing Unit (AIPU) designed for AI inference acceleration in HPC applications
- General-purpose processor (GPP) optimized for HPC workloads in European supercomputers
These chiplets will be developed and taped-out in advanced CMOS technology nodes, overcoming the limitations of traditional monolithic chips by offering greater efficiency, scalability, and cost advantages.
To ensure the success of these innovations, DARE SGA1 employs a HW/SW co-design approach, using a carefully selected set of European HPC and AI applications to guide development. A complete SW stack, optimized for DARE SGA1 HW, will be built in parallel with HW design, leveraging early access to RISC-V HW emulation and simulation. Additionally, DARE will include exploratory pathfinding SW and HW design activities for the immediate future and roadmapping efforts to conduct scalability studies for future supercomputer deployments.