Design of Digital Circuit for a Passive RFID Tag

The low power design of the digital block for apassive RFID tag, conforming to the ISO/IEC 15693 standard, ispresented in this work. The fundamental digital design flow andtypical low-power techniques are discussed. These techniqueswere efficiently exploited in this design to reduce the powerconsumption of the block about 95% with respect to the initialdesign, down to 10 μW. Design of Digital Circuit for a Passive RFID Tag.