Code Multiplexed VLSI Test Architecture for SOC Testing

This work presents a code multiplexed test architecture for system-on-a-chip (SOC) testing utilizing simultaneous test data from test generators (TGs) transaction on common bus to the embedded core in the SOC. To improve the SOC testing performance without increasing the testing channel resources and complexity, this work presents an efficient test architecture that exploits parallelism in core-level testing, resulting in shorter testing time and higher concurrency on a shared test bus. The proposed code division multiple access (CDMA) enables multiple concurrent transactions on a shared bus. The CDMA utilizes n-bit orthogonal code for n-embedded
cores, which exploits parallel testing with reduced number of test buses and complexity. The multiple access mechanism of the CDMA improves real-time communication between multiple embedded cores or semiconductor intellectual property (SIP) blocks on a shared bus. This technique is experimentally verified with Xilinx’s Virtex-5 XC5VLX50FF676 and Xilinx ISE 12.1 Software environment.