Hardware-Friendly Random Forest Classification of iEEG Signals for Implantable Seizure Detection

Abstract

Early and accurate detection of epileptic seizures is an extremely important therapeutic goal due to the severity of complications it can prevent. To this end, a low-power machine learning-based seizure detection implemented on an FPGA is proposed in this paper. Feature extraction is performed using time domain features which exhibit low hardware implementation complexity as well as high classification performance. A comparison between a Random Forest and a linear Support Vector Machine classifier has been conducted leading to the superior performance of the Random Forest. In addition, the hyperparameters of the Random Forest classifier are optimized to reach the best classification performance as well as to maintain the hardware implementation complexity sufficiently low for medical devices implants. The proposed seizure detector is implemented on a Cyclone V FPGA of the ALTERA DE10-standard board and tested on iEEG signals of six patients from the Bern University Hospital. FPGA implementation results demonstrate 100% seizure detection sensitivity as well as better specificity and faster seizure detection compared to recently published works using random forest classification. The FPGA dynamic power consumption is 0.59 mW which is acceptable for low-power implantable devices.

Materials

The conference paper presented in IEEE-EMBS IECBES 2022 as well as VHDL and MATLAB codes are included in this file. Necessary scientific explanations and details of the algorithms are provided in the manuscript. 

MATLAB codes are developed to perform feature extraction in time-doamin and seizure classificatrion using RF and SVM classifiers.

VHDL codes are developed to execute RTL implementation of the algorithm. There are two seprated .vhdl files for feature extraction and RF classifier implementation. A testbench .vhdl file is also given to test the design.