Published March 30, 2023 | Version CC BY-NC-ND 4.0
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Implementation of LVCMOS based 4 Bit FPGA Based ALU on SP 701 Board for New Digital Age Technologies

  • 1. Department of Computer Science, Dev Sanskriti Vishwavidyalaya, Haridwar (Uttarakhand), India
  • 2. Dean, School of Technology, Management & Communication, Dev Sanskriti Vishwaviidyalya, Hardwar (Uttarakhand), India
  • 3. Director, Uttarakhand Science Education and Research Centre (USERC), Dehradun (Uttarakhand), India.
  • 4. Uttarakhand Science Education & Research Centre (USERC) Dehradun (Uttarakhand), India.

Contributors

  • 1. Department of Computer Science, Dev Sanskriti Vishwavidyalaya, Haridwar (Uttarakhand), India

Description

Abstract: Objectives: The 4-bit ALU of a RISC processor is designed as shown by the researcher in this paper. The 4-bit ALU used in this work can perform 2 4 = 16 various arithmetic and logical operations, including addition, subtraction, multiplication, and division as well as logical AND, OR, NAND, NOR, NOT, XOR, XNOR, INCREMENT, DECREMENT, ROTATE LEFT, and ROTATE RIGHT. Methods: The author used the Vivado simulation tools with the Verilog HDL language to build the FPGA-based ALU, and the SP701 Spartan FPGA board was used to implement the entire design. It has been implemented to use energy-efficient IO standard approaches. Findings: By calculating the overall power usage at the pre- and post-levels, this research has developed a new method for building energy-efficient FPGA-based ALUs. Author utilized Vivado simulation tool for this investigation. The SP701 FPGA board has also been used to implement this idea. Novelty: The Internet of Things and other emerging digital era technologies will undoubtedly benefit from this research work, and its energy efficient design will support environmental initiatives.

Notes

Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP) © Copyright: All rights reserved.

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References

  • S.Pandey G.Verma B. Das T.Kumar M.Dhankar "Energy Efficient Solar Charge Sensor Design Using Spartan-6 FPGA "Gyancity Journal of Electronics and Computer Science, Vol.1, No.1, pp.18-24, September 2016 ISSN: 2446–2918 DOI: 10.21058/gjecs.2016.11004.
  • A Saxena, A Bhatt, P Gautam, P Verma, C Patel,"High Performance FIFO Design for Processor through Voltage Scaling Technique" In Indian Journal of Science and Technology Vol 9(45), DOI: 10.17485/ijst/2016/v9i45/106916, December 2016
  • Swiegers, W., Johan H.R. Enslin, 1998. An Integrated Maximum Power Point Tracker for Photovoltaic Panels. [Online], Available: IEEE Explore database. [20th July 2006].
  • Hussein, K.H, I. Muta, T. Hoshino and M. Osakada, 2006. Maximum Photovoltaic Power Tracking: an algorithm for rapidly changing atmospheric conditions. [Online], IEEE Proceeding of Generation, Transmission and Distribution, pp: 142.
  • A Saxena, S Gaidhani, A Pant, C Patel "Capacitance Scaling Based Low Power Comparator Design on 28nm FPGA" in International Journal of Computer Trends and Technology (IJCTT) – Volume X Issue Y- Month 2015
  • A Saxena, C Patel, M.Khan "Energy Efficient CRC Design for Processor ofWorkstation, and Server using LVCMOS " in Indian Journal of Science and Technology, Vol 10(4), DOI: 10.17485/ijst/2017/v10i4/110890, January 2017.
  • A.Singla,A.Kaur, B.Pandey "LVCMOS based energy efficient solar charge sensor design on FPGA" in Power Electronics (IICPE), 2014 IEEE 6th India International Conference DOI: 10.1109/IICPE.2014.7115800.
  • M. Renovell, J. Figueras, Y. Zorian, "Test of RAM-Based FPGA: Methodology and Application to the Interconnect", 15th IEEE VLSITest Symposium, pp. 230-237, 1997, Monterey, CA.
  • R Roux, G. Schoor,P. Vuuren" Block RAM-based architecture for realtime reconfiguration using Xilinx R FPGAs" Research Article – SACJ 56, July 2015.
  • C.Patel, P.Verma, P. Agarwal, A.Omer,B. Gururani, S.Verma "Designing Green ECG Machine Basedon Artix-7 28nm FPGA " Gyancity Journal of Engineering and Technology,Vol.3, No.1, pp. 36- 41, January 2017ISSN: 2456-0065 DOI:10.21058/gjet.2017.31006
  • W.K. Huang and F. Lombardi, "An Approach for Testing Programmable/Configurable Field Programmable Gate Arrays,14th IEEE VLSI Test Symposium, pp. 450-455, Princeton, NJ,USA, May 1996.
  • A Saxena, S Sharma, P Agarwal, C Patel "SSTL Based Energy Efficient FIFO Design for High Performance Processor of Portable Devices" in International Journal of Engineering and Technology (IJET)Vol 9 No 2 Apr-May 2017DOI: 10.21817/ijet/2017/v9i2/170902113.

Subjects

ISSN: 2277-3878 (Online)
https://portal.issn.org/resource/ISSN/2277-3878
Retrieval Number: 100.1/ijrte.F74980311623
https://www.ijrte.org/portfolio-item/F74980311623/
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Publisher: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP)
https://www.blueeyesintelligence.org/