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Published April 9, 2022 | Version v1
Conference paper Open

Experimental Results of Vectorized Posit-Based DNNs on a Real ARM SVE High Performance Computing Machine

  • 1. Università di Pisa
  • 2. MMI spa

Description

With the pervasiveness of deep neural networks in scenarios that bring real-time requirements, there is the increasing need for optimized arithmetic on high performance architectures. In this paper we adopt two key visions: i) extensive use of vectorization to accelerate computation of deep neural network kernels; ii) adoption of the posit compressed arithmetic in order to reduce the memory transfers between the vector registers and the rest of the memory architecture. Finally, we present our first results on a real hardware implementation of the ARM Scalable Vector Extension.

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Additional details

Funding

EPI SGA1 – SGA1 (Specific Grant Agreement 1) OF THE EUROPEAN PROCESSOR INITIATIVE (EPI) 826647
European Commission
TEXTAROSSA – Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale 956831
European Commission