Published June 29, 2021
| Version 2.1
Software
Open
Time-Sliced Architecture for Efficient Accelerator to Detrend High-Definition Electroencephalograms
Description
The implemented netlist files, and allied simulation code associated with the publication, "Time-Sliced Architecture for Efficient Accelerator to Detrend High-Definition Electroencephalograms"
Xilinx System Generator 2016.4 and Vivado 2016.4 were used for the design and implementation of the hardware accelerator.
Please see README.md for more information.
contact : raks0009@gmail.com
Files
README.md
Files
(2.1 GB)
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2.1 GB | Download |