Published January 30, 2022 | Version v1
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DSP TMS320C6678 Based SHVC Encoder Implementation and its Optimization

  • 1. , University of Sfax, National Engineering School of Sfax Electronics and Information Technology Laboratory, LETI Sfax, Tunisia
  • 1. Publisher


The programmable processors newest technologies, as for example the multicore Digital Signal Processors (DSP), offer a promising solution for overcoming the complexity of the real time video encoding application. In this paper, the SHVC video encoder was effectively implemented just on a single core among the eight cores of TMS320C6678 DSP for a Common Intermediate Format (CIF)input video sequence resolution(352x288). Performance optimization of the SHVC encoder had reached up 41% compared to its reference software enabling a real-time implementation of the SHVC encoder for CIF input videos sequence resolution. The proposed SHVC implementation was carried out on different quantization parameters (QP). Several experimental tests had proved our performance achievement for real-time encoding on TMS320C6678.


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Journal article: 2277-3878 (ISSN)


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