Low Latency On-Board Data Handling for Earth Observation Satellites using Off-the-Shelf Components

Satellite Earth Observation (EO) is nowadays receiving significant attention. In this regard, the latency of EO products provision to the ground segment is undoubtedly among the first key performance indicators for these systems. Traditionally, small EO satellites rely on the flight segment for raw data acquisition and compression, while the image processing tasks are performed at the ground segment. The latency of raw data transmission prevents such systems from achieving better than Near Real-Time (NRT) delivery of EO products, which are typically available to the end-user after 1h to 3h from acquisition time.
The European Union Horizon 2020 EO-ALERT project aims at significantly reducing this latency by moving all the critical processing tasks on the flight segment and accelerating them using high-performance commercial off-the-shelf (COTS) devices. The resulting architecture minimizes the amount of transmitted data and eliminates ground-based data processing from the EO data chain, hence achieving actual real-time product delivery in less than 5min with optical and Synthetic Aperture Radar (SAR) data.
The centerpiece of the proposed architecture is the embedded CPU Scheduling, Compression, Encryption, and Data Handling (CS-CEDH) Subsystem, essentially fulfilling two roles: 1) acquire and move images and products among the image processing and communications subsystems, therefore also coordinating their tasks; 2) compress and encrypt the input and output data with different settings depending on the mission requirements. From an optimal design and resource allocation perspective, these aspects are complementary: while the former is software-focused, aiming at maximizing modularity, flexibility, and dynamic scalability, required by the inherent system-level real-time event-driven nature of the CPU Scheduling processes, the latter represents an intrinsically highly-specialized, computationally expensive data-processing function, better suited for hardware implementation. In order to achieve the overall goal of minimizing the system-level latency, it is therefore mandatory to effectively co-design a mixed hardware/software solution, leveraging the performance of state-of-the-art COTS Multi-Processor System-on-Chip (MPSoC) devices featuring a Processing System (PS) directly interfaced to a Programmable Logic (PL) unit. Such platform enables, thanks to state-of-the-art Electronic Design Automation (EDA) tools, to obtain a Register-Transfer Level (RTL)model (to be deployed on the PL unit) directly from a high-level hardware-friendly software model through High-Level Synthesis (HLS), thereby effectively shifting from a software-only design to a more efficient and high-performance hybrid hardware/software one, without sacrificing run-time tuning of compression and encryption parameters and still meeting all the system-level requirements. The PS hosts the scheduling and data handling software and seamlessly off-loads data-intensive tasks to the PL, allowing to dedicate most of the CPU resources to compress, encrypt and transmit small, high-priority EO products (alerts) with very low latency while also processing larger data (e.g., generated images) with high-throughput.
Here we present the first promising results of this design methodology applied to the CS-CEDH Subsystem of the EO-ALERT architecture. In particular, its contribution to the alert provision latency is under 1s in every foreseen application scenario. Simultaneously, the hardware compression/encryption accelerator enables a 6 to 7-fold speed-up compared to a software-optimized implementation when also compressing, encrypting, and transmitting the processed images.