Evaluation of new generation rad-hard many-core architecture for satellite payload applications

Computing power requirements of space applications, in particular for payload functions, are constantly rising with the objective of increasing the number of processing operations that can be carried out on board to achieve higher spatial, spectral, temporal and radiometric resolution. Moreover, next generation projects are seeking a breakthrough by embedding new innovative processing to gain efficiency, flexibility and autonomy, putting more emphasis on the necessity to have powerful processing components.
Two kinds of solutions are available to meet the need of on-board processing power: radiation tolerant COTS hardware subject to component unavailability issues, or space dedicated hardware with lower capabilities. Instead, the RC64 component from Ramon.Space proposes a good compromise, being radiation-hardened (Rad-Hard) and proposing significant processing capacity with 64 DSP cores.
The RC64 component is a many-core radiation-hardened processor, built around spatial DSPs [1], and designed for applications requiring high computing power and very high speed processing [2][3]. This component has a massively parallel architecture that offers processing performances close to FPGAs or specialized ASIC, but also provides the flexibility of software programming and low power consumption. However, its architecture requires rethinking the algorithms in order to make the most of the RC64 capabilities.
Last few years, CNES has been working on the evaluation of this component for different space applications. As part of this effort, a study has been launched to evaluate the suitability of using the RC64 component with high complex algorithms.
The algorithm used on this study is based on the latest CCSDS 123 standard [4], which introduces, among other new features, near-lossless compression. However, this standard has been designed in a sequential way, which means that modifying the execution model is necessary for parallel operation, and it was a required step before any attempt at efficient implementation on a many-core.
Thus, the first step was to familiarise with this component through micro-benchmarks, to learn good practices and gain technical knowledge for an efficient use of the RC64 programming model, as well as on its architectural specificities: the impact of DSPs in parallel, the memory hierarchy and the hardware multi-tasking scheduler needed to be analysed to achieve good processing performances. Then we applied this knowledge to the considered CCSDS algorithm, testing different configurations, in both the prediction and the encoding steps which have an impact on parallelisation performance and memory usage, so as to realise a preliminary implementation of the CCSDS-123.0-B-2 that tried to achieve efficient performance and scalability on the RC64.
In this paper, we propose an overview of the RC64 architecture and a description of the methodology used to parallelise efficiently the application on this target. Then, we present the results of the implementation as well as the conclusions of the evaluation.
[1] CEVA DSP processors for MacSpace, MacSpace Symposium and Summer Seminar, 2016
[2] RC64: High Performance Rad-Hard Manycore, Aerospace Conference, 2016 IEEE
[3] MacSpace / RC64 architecture, MacSpace Symposium and Summer Seminar, 2016
[4] Low-Complexity Lossless and Near-Lossless Multispectral & Hyperspectral Data Compression, Recommended Standards. CCSDS-123.0-B-2. Blue Book, 2019