Automated Intrinsic Support for ISA Extensions: Enhancing Software Generation for RISC-V and Beyond

Software development is a significant portion of the effort in today’s SoC designs, making software productivity a major challenge. High-level programming languages and extensive libraries address this challenge, but another effective solution is the use of code generators. Special and customized CPU instructions are crucial for low-level tasks (e.g. CSR configuration) and compute-intensive applications like machine learning inference, as they help meet Power, Performance, and Area (PPA) requirements. However, these instructions often cannot be automatically inferred by compilers from high-level languages like C or RUST and must be explicitly coded using intrinsic notations. Code generation offers a promising solution by supporting various intrinsics across different CPU cores and variants, enabling portable, automated embedded software development. This paper discusses the key drivers and challenges in intrinsic design and proposes a structured approach to generating portable code with intrinsic notations using formal models for the software and the involved cores. This approach effectively addresses productivity challenges while meeting PPA constraints and has been successfully applied to code generation for commercially used RISC-V variants, demonstrating its industry relevance.