Published November 20, 2024 | Version v1

Special Session: A Mixed Simulation-, Emulation-, and Formal-Based Fault Analysis Methodology for RISC-V

  • 1. ROR icon Infineon Technologies (Germany)
  • 2. ROR icon Rheinland-Pfälzische Technische Universität Kaiserslautern-Landau
  • 3. ROR icon Technical University of Munich

Contributors

  • 1. Infineon Technologies (Germany)
  • 2. ROR icon Technical University of Munich

Description

As the semiconductor industry rapidly expands, there is a need for new development methods, especially in the domain of safety-critical designs. The ISO 26262 standard plays a crucial role in the automotive industry by requiring systems to operate safely and reduce the chance of critical failures. Advanced, automated approaches are essential to meet these challenges effectively. This paper presents an automated framework for safety verification using the principles of model-driven architecture, which aims to increase the efficiency, quality, and trustworthiness of these systems. It introduces the concept of creating models with different levels of granularity for various components of a design such as gate-level models for the safety-critical parts and Register-Transfer Level (RTL) models for the rest of the designs. The innovation includes adding fault injectors to these models to inject faults directly in the design. Through a holistic generation flow, various safety verification techniques have been explored, including methods based on simulation, emulation, and formal verification. The effectiveness of these methods has been demonstrated in many different industrial desion applications.

Notes

Accepted version. ©2024 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Published as: E. Kaja et al., "Special Session: A Mixed Simulation-, Emulation-, and Formal-Based Fault Analysis Methodology for RISC-V," 2024 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Didcot, United Kingdom, 2024, pp. 1-6, doi.org/10.1109/DFT63277.2024.10753503

Files

Special_Session_A_Mixed_Simulation_ Emulation_and_Formal-Based_Fault_Analysis_Methodology_for_RISC-V.pdf

Additional details

Identifiers

ISBN
979-8-3503-6688-4
ISBN
979-8-3503-6689-1
ISSN
2765-933X
ISSN
2576-1501

Funding

European Commission
ISOLDE - High Performance, Safe, Secure, Open-Source Leveraged RISC-V Domain-Specific Ecosystems 101112274
Federal Ministry of Education and Research
Scale4Edge 16ME0122K