HiDALGO2 D3.6 Innovative HPC Technologies and Benchmarking

The report outlines trends in innovative High Performance Computing architectures associated with established HPC processor manufacturers. This analysis primarily concentrates on the advanced AMD EPYC 9004 and 9005 series processors, including the novel 128-core and 192-core models based on the Zen 5 and Zen 5c microarchitectures, together with the Intel Xeon 6 (Granite Rapids) processors, and includes a discussion of the testbeds used. The Wildfires pilot serves as a foundation for evaluating these architectures. The simulation relies on the WRF-SFIRE model, a coupled fire-atmosphere model based on the Weather Research and Forecast (WRF) model, in which an empirical fire spread model combined with a fuel moisture parameterisation is dynamically coupled with local meteorology. Following the description of the use case, the methodology for benchmarking the processors is outlined, covering the benchmark procedure, resource binding and allocation, and the profiling and energy measurement tools employed. The performance and energy evaluation focuses on the WRF-SFIRE code executed on AMD EPYC platforms representing the Genoa, Genoa-X, and Turin generations, as well as on Intel Granite Rapids processors, using configurations from one to four compute nodes. A central element of this work is the assessment of hybrid MPI+OpenMP execution, where the number of OpenMP threads per MPI rank is varied while the total core count is kept constant. The results reveal that the runtime minimum is consistently located at four OpenMP threads per rank across all evaluated AMD platforms and node counts, confirming that the optimal balance is largely independent of system scale. The cross-platform comparison examines runtime, average node power demand, and total energy consumption, while the profiling and MPI analysis explains the observed behaviour through cache efficiency, memory throughput, and communication characteristics, including the influence of domain decomposition on halo exchange volume. Finally, the report explores the performance, scalability, and parallel scheduling of sparse transformer architectures for large language model inference on CPU-based HPC systems. By replacing dense kernels with Sparse Matrix-Matrix Multiplication and Sampled Dense-Dense Matrix Multiplication, sparsification reduces both memory overhead and computational cost. The analysis demonstrates the theoretical potential of scheduling independent matrix operations concurrently across the transformer pipeline, while identifying the practical limitations imposed by resource contention, thread affinity behaviour in vendor libraries, and static partitioning constraints.