Published December 11, 2025 | Version v1.0.0
Software Open

OpenSiliconHub: ChaCha20 Hardware Core

Authors/Creators

  • 1. Kalasalingam Academy of Research and Education

Description

A parameterized, area-efficient Verilog hardware implementation of the ChaCha20 stream cipher, supporting ChaCha8, ChaCha12, and ChaCha20 variants. This release includes synthesizable RTL, testbenches validated against RFC 8439, synthesis scripts, performance analysis, reproducibility artifacts, and a technical paper.

Notes

If you use OpenSiliconHub's ChaCha20 hardware core, please cite this release.

Files

MrAbhi19/OpenSiliconHub-v1.0.0.zip

Files (1.4 MB)

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Additional details

Related works

Is supplement to
Software: https://github.com/MrAbhi19/OpenSiliconHub/tree/v1.0.0 (URL)

Software

Repository URL
https://github.com/MrAbhi19/OpenSiliconHub