Published November 5, 2025
| Version v1
Performance Improvement in Sub-2nm Node Nanosheet-FETs Through Optimization of Spacer Interface and Dopant Activation
Authors/Creators
- 1. IMEC
-
2.
KU Leuven
Description
Nanosheet-based FETs (NSFETs) are replacing FinFETs beyond the 2nm technology node. In these architectures, dopant deactivation and interface carrier trapping become increasingly prominent. This study investigates the impact of phosphorus (de)activation and SiN/Si interface traps in 45 nm gate pitch NSFETs under varying thermal budgets. Through a combination of targeted experiments and TCAD simulations, we predict that mitigating interface traps and optimizing dopant activation in source/drain regions leads to a factor 2.47 increase in drive current at fixed off-current. Finally, we propose a processing alternative to minimize interface trap density in nanosheet channels.
Files
ESSERC25_AP_submitted.pdf
Additional details
Funding
Dates
- Submitted
-
2025-04-11