FPGA Based Data Smoother for Sensor Data
In this project it should be tested to use a sensor smoothing algorithm on an FPGA to directly reduce the noise on raw sensor data in general. Noise is a large issue for all high energy physics detectors and it is quite common to use some kind of pre-processing like clustering to reduce the needed bandwidth and reduce the later needed processing complexity due to combinatorics. For sensor data from vibrations monitoring systems the reduction of noise is the main issue.
Different smoothing algorithms will be investigated and afterwards implemented on a modern Cyclon V SOC FPGA. The data source will be a vibration sensor foreseen for monitoring the hard drives of the LHCb computing farm.
To realize the system the processing of fix-point calculations in HDL will be studied and simulated in ModelSim. Furthermore, a test bench for the system has to be written, to test the different smoothing algorithms. Afterwards the performance of the designs will be tested with real sensor data.
The primary output of any experiment in which significant information is to be extracted is information which measures the phenomenon under observation. Indistinguishable from this information are random errors which, regardless of their source, are usually described as noise. Of importance to the experimenter is the removal of as much of this noise as possible without, at the same time, overly degrading the underlying information.
In this experimental work, the information from vibration sensor is obtained in the form of four-column table of numbers. This paper is concerned with computational method for the removal of the random noise from such information as well as implementation of this method in HDLs (Hardware Description Languages) and run the algorithm on an FPGA (field programmable gate array).
In this project, random noise from vibration sensor’s data is removed using the smoothing algorithm, which is called moving average. This algorithm is implemented inside an average block using VHDL and Verilog languages. The average block is using binary fixed point math library (fixed point addition and fixed point division) as well as Finite State Machine (FSM) and this is ran through the pipeline on an FPGA board.
Finally, we show the outcome of smoothing data from the vibration sensor and what was the influence of the implemented smoothing method using graphs, histograms and simulation results.
Keywords: FPGA, smoothing data, VHDL, Verilog, average block, fixed point addition, fixed point division, sensor data.