Published April 25, 2017
| Version v1
Journal article
Open
FPGA BASED SDR FOR DPLL APPLICATION
Authors/Creators
Description
To design and develop a system on chip reconfigurable modules Field Programmable Gate Array (FPGA) provides a way with high performance. In this paper, FPGA architecture is proposed, which would be a starting point for developing an efficient Software Defined Radio (SDR) architecture for recovering audio signals from digitally modulated frequency wave. At the modulator and demodulator sections, a Digital Frequency Generator (DFG) is applied for generating the carrier wave by exploiting the quarter wave symmetry of sine or cosine waves with dynamic range of more than 90dB.
Files
20150288-dfm-dpll-fpga-sdr.PDF
Files
(829.3 kB)
| Name | Size | Download all |
|---|---|---|
|
md5:17aafdae1f45d8a5207b0e0446c29224
|
829.3 kB | Preview Download |