D4.2 Interim report on the unified programmable data plane layer of DESIRE6G
Contributors
Project leader:
Project members:
- Velasco, Luis1
- Ruiz, Marc1
- Comellas, Jaume1
- Careglio, Davide1
- Barzegar, Sima1
- Prat, Josep1
- Gombos, Gergő2
- Mallouhi, Hiba2
- Hudoba, Peter2
- Gucciardo, Michele3
- Agoustures, Mark4
- Lefebvre, Vincent
- Pihan, Alexis
- Sgambelluri, Andrea5
- Alhamed, Faris5
- Castoldi, Piero5
- Paolucci, Francesco6
- Abu Bakar, Rana6
- Kis, Dávid7
- Mihály, Attila
- Chackravaram, Kiran8
- Pryor, Simon9
- Castellanos, German8
- Nanos, Anastassios10
- Xie, Hongjie11
Description
This document presents an interim report detailing the implementation and development of the unified data plane layer within the DESIRE6G architecture, as part of the work conducted in WP4 from months 12 to 23. Building upon the requirements and architecture defined in WP2, the report describes the initial prototypes of the different components, their preliminary evaluation results, current limitations, and plans for improvement. It covers enhancements to network service deployment, data plane techniques, programmable traffic management, monitoring solutions, and hardware accelerators. These components collectively address performance, latency, and resource-sharing challenges, enabling a cloud-native approach to packet processing. The document assumes familiarity with DESIRE6G terminology and architecture and complements earlier deliverables D2.2 and D4.1.
Files
DESIRE6G_D4_2_Interim_report_on_the_unified_programmable_data_plane_layer_1.1.pdf
Files
(5.7 MB)
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