The NEORV32 RISC-V Processor

What's Changed

• ⚠️ rework CFU (remove R5-type instructions) by @stnolting in https://github.com/stnolting/neorv32/pull/971
• Rework (and auto-generate) file-list files by @stnolting in https://github.com/stnolting/neorv32/pull/972
• [docs] fix spelling by @NikLeberg in https://github.com/stnolting/neorv32/pull/975
• [vivado_ip] fix error when AXI port is unconnected by @stnolting in https://github.com/stnolting/neorv32/pull/976
• [vivado_ip] fix unconnected variable-size inputs by @stnolting in https://github.com/stnolting/neorv32/pull/978
• [vivado_ip] constrain minimal size of variable-sized output ports by @stnolting in https://github.com/stnolting/neorv32/pull/980
• Minor RTL edits by @stnolting in https://github.com/stnolting/neorv32/pull/984
• :warning: reorganize core RTL files :warning: by @stnolting in https://github.com/stnolting/neorv32/pull/985
• [rtl] minor timing and area optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/990
• RTL reworks, cleanups and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/996
• :bug: fix minor regression bug; minor RTL optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/998

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.10.2...v1.10.3