Published May 14, 2026 | Version v1.13.1
Software Open

stnolting/neorv32: v1.13.1

Description

What's Changed

  • Two write-back D-cache correctness fixes (fence.i + AMO bypass) by @14sea in https://github.com/stnolting/neorv32/pull/1540
  • [image_gen] Pass a flattened ELF binary instead of parsing the ELF itself by @stnolting in https://github.com/stnolting/neorv32/pull/1541
  • ⚠️ [cpu] rework trap CSRs (mcause, mtval, mtinst) by @stnolting in https://github.com/stnolting/neorv32/pull/1542
  • [rtl] minor fixes, edits and cleanups (PMP, TWD, bus) by @stnolting in https://github.com/stnolting/neorv32/pull/1543
  • Rework on-chip debugger by @stnolting in https://github.com/stnolting/neorv32/pull/1544
  • ✨ [sim] add JTAG/DMI tests to testbench by @stnolting in https://github.com/stnolting/neorv32/pull/1545
  • ✨ [Zihpm] add support for all 29 hardware performance monitors by @stnolting in https://github.com/stnolting/neorv32/pull/1546
  • 🐛 [pmp] fix reserved permissions and address/mask storage by @stnolting in https://github.com/stnolting/neorv32/pull/1549
  • ✨ add support for RISC-V Zbc ISA extension by @stnolting in https://github.com/stnolting/neorv32/pull/1550
  • ✨ add support for time[h] CSRs by @stnolting in https://github.com/stnolting/neorv32/pull/1551
  • remove riscv-arch-test folder and submodule by @stnolting in https://github.com/stnolting/neorv32/pull/1552
  • [trace] add RVC trace logging by @stnolting in https://github.com/stnolting/neorv32/pull/1553

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.13.0...v1.13.1

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stnolting/neorv32-v1.13.1.zip

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