Two Methods of the Clock Jitter Measurement Aimed at Embedded TRNG Testing

In modern cryptographic systems, security is based on quality and unpredictability of confidential keys. These keys are generated in random number generators using random physical phenomena appearing inside the cryptographic system on chip. The most frequently used source of randomness in digital devices is the jitter of clock signals generated inside the device in ring oscillators, self-timed rings, RC oscillators, phase-locked loops (PLLs), etc. The quality and unpredictability of generated numbers depends on the quality and the size of the clock jitter. It is therefore a good practice to monitor this jitter continuously using some embedded jitter measurement method. The measured jitter parameters can be then used as input parameters of the stochastic model used to estimate entropy, which characterizes unpredictability of generated numbers. In this paper, we present and compare two methods of embedded jitter assessment based on the measurement of the variance of counter values, obtained by counting the periods of the jittery clock during a time interval defined by a reference clock generated in the same device. Besides comparing obvious design results such as area, speed, and power consumption, we observe and discuss the impact of the two embedded variance measurement methods on the clock jitter itself, and compare the behavior of the two clock generators used as sources of randomness with and without clock variance measurement circuitry, and with and without additional logic such as an AES cipher, which perturbs the variance computation, as it is the case in most cryptographic embedded systems. This comparison is very important for a good estimation of the low entropy bound from the measurement results.