Published July 30, 2024 | Version CC-BY-NC-ND 4.0
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Design of 125-Level Asymmetrical Multilevel Inverter with Reduced Switch Count

Creators

  • 1. Department of Electrical & Electronics Engineering, Sri Venkateswara University College of Engineering, Sri Venkateswara University, Tirupati, India.

Contributors

Contact person:

Researcher:

  • 1. Department of Electrical & Electronics Engineering, Sri Venkateswara University College of Engineering, Sri Venkateswara University, Tirupati, India.

Description

Abstract: This paper provides a unique reduced component-count-efficient topology for 125-level asymmetrical multilevel inverter. The proposed design uses asymmetric DC sources and an H-bridge to produce an output voltage that can reach a maximum of 125 levels. The design and development of a multi-level inverter with a stacked half-bridge architecture that generates a 125-level output with excellent power quality is the object of the current research. The MOSFETs are triggered using a fundamental frequency switching technique that has been modified for output voltage level control. At its output, the level production circuit exclusively generates positive levels. Look-up tables are employed to regulate MOSFETs, and an H-bridge circuit is used to create polarities. 125 levels of output result in a nearly sinusoidal voltage waveform, which will give a nearly sinusoidal voltage waveform without the use of filters. The proposed work is Simulated in MATLAB/Simulink software.

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Additional details

Identifiers

DOI
10.35940/ijsce.H9914.14030724
EISSN
2231-2307

Dates

Accepted
2024-07-15
Manuscript received on 03 June 2024 | Revised Manuscript received on 05 July 2024 | Manuscript Accepted on 15 July 2024 | Manuscript published on 30 July 2024.

References

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