FVF-Based Low-Dropout Voltage Regulator with Fast Charging/Discharging Paths for Fast Line and Load Regulation

This article proposes an LDO regulator structure based on the CASFVF cell. The structure, designed with standard 65nm CMOS technology, uses a gain-boosting technique, adaptive biasing, and includes fast settling paths to increase the regulation loop gain and quickly charge/discharge the parasitic capacitance of the pass transistor gate. This leads to a fast transient response with low quiescent power consumption. An analysis of the small signal behavior of the proposed structure demonstrates its adequate stability in all cases making use of nested-miller compensation. The experimental results show small voltage spikes and a short settling time for large transient line and load variations, even when the rise and fall times decrease to 1 μs.