Influence of the surface morphology on the channel mobility of lateral implanted 4H-SiC(0001) metal-oxide-semiconductor field-effect transistors

The influence of the surface morphology on the channel mobility of 4H-SiC metal-oxidesemiconductor field effect transistors annealed under two different conditions is discussed. The devices were fabricated using post-implantation annealing at 1650 C. In particular, while the use of a protective capping layer during post-implantation annealing preserved a smooth 4H-SiC surface resulting in a channel mobility of 24 cm2 V1 s1, a rougher morphology of the channel region (with the presence of surface macrosteps) was observed in the devices annealed without protection, which in turn exhibited a higher mobility (40 cm2 V1 s1). An electrical analysis of SiO2/SiC capacitors demonstrated a reduction of the interface state density from 7.21011 to 3.61011 cm2 eV1, which is consistent with the observed increase of the mobility. However, high resolution transmission electron microscopy showed an almost atomically perfect SiO2/4HSiC interface. The electrical results were discussed considering the peculiar surface morphology of the annealed 4H-SiC surfaces, i.e., attributing the overall reduction of the interface state density to the appearance of macrosteps exposing non-basal planes.