Journal article Open Access
Manouras, Vasileios; Papananos, Ioannis
In this paper the design, analysis and implementation of a 3-stage, broadband power amplifier (BPA), is presented. The device is suitable for medium-distance wireless and wireline gigabit communication in the D-band (110 – 170 GHz). A pseudo-differential cascode topology is adopted for each stage leading to optimized broadband performance. The PA is integrated in a 0.13 μm SiGe BiCMOS technology with f T /f max = 250/370 GHz, achieving a saturation output power P sat > 9 dBm and a maximum large-signal power gain G P > 29.5 dB, over the entire D-band. The chip size is 1.150 × 0.467 mm 2 including all pads.
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