Published February 24, 2023
| Version 1.0.0
Dataset
Open
Figures of merit that characterize silicon gate-all-around nanowire FETs affected by line edge roughness variability
Authors/Creators
- 1. Universidade de Santiago de Compostela
Description
Off-current, threshold voltage, sub-threshold slope and on-current values for two silicon gate-all-around nanowire FETs affected by line edge roughness (LER) variability, a 22 nm gate length device and a 10 nm gate length one. The LER profile that characterizes the roughness deformation is also included in the dataset. Different correlation length (CL) and root mean square (RMS) heights values are characterized.
Notes
Work supported by the Spanish MICINN, Xunta de Galicia, and FEDER Funds under Grants PLEC2021-007662, RYC-2017-23312, PID2019-104834GB-I00, ED431F 2020/008 and ED431C 2022/16.