ELECTRONICS & ELECTRICAL DOMAIN
Published February 15, 2023 | Version v1
Journal article Open

Performance Analysis of Full Adder using Ganged CMOS Threshold Element with Different Technologies

Creators

  • 1. Rajeev Gandhi Memorial College of Engineering and Technology, Nandyal, India

Description

A threshold gate is a type of digital logic gate that has multiple inputs and a single output. The output of the gate is determined by the number of inputs that are at a high (or 1) state. The threshold value, or number of inputs required to be at a high state, is set by the design of the gate. These gates are used in digital circuits to perform Boolean logic operations and are commonly used in computer processors and other digital devices. The inputs are multiplied by weights (Wi) and added to produce a resultant sum, which is then compared with threshold value ‘T’ to get the output Y. The values of weights and threshold should be real, finite, positive or negative numbers. In this paper we have designed a Ganged Complementary Metal Oxide Semiconductor Field Effect Transistor (GCMOS) 1- bit Full-Adder (FA) circuit. For all the simulations, A, B and Cin are taken as three binary inputs. The major advantage of this Ganged CMOS logic based FA circuit is its simplicity and lower transistor count. The circuit is simulated using Microwind tool with 50nm, 70nm and 90nm CMOS technologies.

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References

  • 1. Venkataiah, C., Chennakesavulu, M., Ramanjaneyulu, N., Rao, Y.M., Sathish, A., Jayamma, M. (2023). Ternary logic full adder circuit using 3×1 multiplexer. Journal of advancement in electronics design, 6(1), 1-9.
  • 2. Venkataiah, C., Ramanjaneyulu, N., Rao, Y. M., Prakash, V. S., Murthy, M. L., & Rao, N. S. (2022). Design and performance analysis of buffer inserted on-chip global nano interconnects in VDSM technologies. Nanotechnology for Environmental Engineering, 7(3), 775-781.
  • 3. Venkataiah, C., Satyaprasad, K., & Jayachandra Prasad, T. (2019). Insertion of an Optimal Number of Repeaters in Pipelined Nano-interconnects for Transient Delay Minimization. Circuits, Systems, and Signal Processing, 38, 682-698.
  • 4. Venkataiah, C., Satyaprasad, K., & Prasad, T. J. (2018). FDTD algorithm to achieve absolute stability in performance analysis of SWCNT interconnects. Journal of computational electronics, 17, 540-550.
  • 5. Venkataiah, C., Setty, D.R., Ramanjaneyulu, N., Rao, Y.M. (2023). Crosstalk peak overshoot analysis of VLSI interconnects. International Journal of Emerging Research in Engineering, Science, and Management, 2(1), 8-12.
  • 6. VENKATAIAH, C., Sathish, A., Ramanjaneyulu, N., & Rao, Y. M. (2023). Peak Overshoot Analysis of On-Chip Interconnects for Different Technologies. Journal of Advancement in Communication System, 6(1).
  • 7. Venkataiah, C., Sathish, A., Ramanjaneyulu, N., Rao, Y.M. (2023). Crosstalk noise analysis of on-chip interconnects. Journal of advancement in communication systems, 6(1), 1-6.
  • 8. Venkataiah, C., Jayamma, M., Rao, Y. M., Ramanjaneyulu, N., & Sathish, A. (2023). An Advanced Technique for Performance Improvement in VLSI Interconnects. Journal of VLSI Design and Signal Processing (e-ISSN: 2581-8449), 9(1), 1-6.
  • 9. Venkataiah, C., Satyaprasad, K., & Prasad, T. J. (2018). Crosstalk Induced Performance Analysis of Single Wall Carbon Nanotube Interconnects Using Stable Finite-Difference Time-Domain Model. Journal of nanoelectronics and optoelectronics, 13(6), 846-855.
  • 10. Venkataiah, C., Satyaprasad, K., & Prasad, T. J. (2018). Signal integrity analysis for coupled SWCNT interconnects using stable recursive algorithm. Microelectronics journal, 74, 13-23.