Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design
Creators
- 1. Imperial College London
- 2. Samsung AI Center Cambridge
- 3. University of Cambridge
- 4. Samsung AI Center Cambridge and Imperial College London
- 5. Samsung AI Cambridge and University of Cambridge
- 6. Cornell University
Description
This repo contains the artifacts for our MICRO'22 paper titled "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design".
The functionality of our hardware accelerator can be evaluated by running Verilog HDL designs and System Verilog testbenches on Vivado design suite.
The accuracy results can be obtained by running our PyTorch programs and the associated Bash scripts.
The power and resource utilization can be obtained by running Synthesis and Implementation using our RTL code and constraint files.
The latency can be obtained by running our custom Python-based performance model.
We also provide all our training log files and Vivado design reports in the link: https://drive.google.com/drive/folders/1zn38AjjQvqHZh-xsmeeIFK2BA-poIRAn?usp=sharing.
Files
NPU_Transformer.zip
Files
(1.4 MB)
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md5:6ff4b82ef8bc133cd7d8ff5da8531595
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