Enhancement in Speed of BCD Adder

Almost all applications work with decimal data and spend the majority of their time doing so. Software implementation of decimal arithmetic is typically 100 times slower than hardware implementation of binary arithmetic. As a result, hardware with decimal arithmetic functionality is necessary. A high-speed binary coded decimal (BCD) adder is proposed in this study. By enhancing parallelism, the suggested adder improves the delay of BCD addition. Two 4-bit binary adders, a carry network, one AND gate, and one OR gate make up the proposed BCD adder's critical path. The programs for the proposed reduced delay BCD adder and the Conventional BCD adder are created in Verilog to compare delays.