PERFORMANCE OPTIMIZATION OF LUT IN FPGA USING CNFET

A Leakage power dissipation is becoming a concern in field-programmable gate arrays (FPGAs) due to scaling in FPGA technology. Field programmable gate arrays (FPGAs) are the implementation platform of choice when it comes to design flexibility. However, the high power consumption of FPGAs (which arises due to their flexible structure), make them less appealing for extreme low power applications hence it is important to investigate ways of reducing FPGA power consumption. This paper proposes an energy efficient dual-threshold CarbonNanotube Field Effect Transistor (CNFET) based architecture of 4-input Look-up Table (LUT), a building block of Field programmable gate arrays. HSPICE simulation based on Berkeley Predictive Technology Model (BPTM) for 32nm channel length, in the CNFET based LUT delay is improved by 95% and  is 98% more leakage power efficient than the LUT implemented in the bulk CMOS.