Journal article Open Access
K. Nathiyadevi; K. Helen Prabha; S. Tamil Selvi
In this digital world, everything is inculcated within technology which increases the importance of memory storage. All the data processed in today’s electronics requires a storage space. The data stored in this memory are extracted & misused which is a serious issue in day today world. This provenly shows that there is a need for enhancement in data security. There are different types of memory storage. Among them portable devices, routers, workstation, personal computer commonly uses SRAM for storage. Due to side-channel leakage power in SRAM, illegal data extraction had become a serious threat.6T SRAM cells are often prone to this power analysis attack . This data attack often happens in standby mode of a memory cell. To provide resiliency to these types of attacks, a symmetric 8T SRAM cell was used which incorporates two more transistors than the conventional 6T cell to significantly reduce the correlation between the stored data and the leakage currents. The main purpose of this paper is to simulate & analyze leakage current distribution for the conventional 6T SRAM cell and a symmetric 8T SRAM cell using Cadence (version 14.6) simulation tool. In addition to this, an effort is made to reduce the leakage current by using the W/L ratio of the transistor. A 16X16 SRAM array using the 6T & 8T SRAM cell is designed. With this design, the reduced standby static power & leakage current of 8T SRAM Cell is compared with convention 6T SRAM Cell. Standard GPDK (generic process design kit) 90nm library in Cadence (version 14.6) simulation tool is used for designing.
|Data volume||22.6 MB|