FPGA Hardware Co-Simulation of Image Encryption using Hybrid Chaotic Maps Based Stream Cipher

In This paper, new model of image encryption is designed. This model using stream cipher based on finite precision chaotic maps. The model designed in efficient way by using Xilinx System Generator (XSG). Pseudo Random Bit Generator (PRBG) depends on chaotic maps is proposed to design Fixed Point Hybrid Chaotic Map-PRBG (FPHYBCM-PRBG). National Institute of Standards and Technology (NIST) randomness measures tested the randomness of the proposed FPHYBCM-PRBG system. The security analysis, such as histogram, correlation coefficient, information entropy, differential attack (NPCR and UACI) are used to analyze the proposed system. Also, FPGA Hardware Co-Simulation over Xilinx SP605 XC6SLX45T provided to test the reality of image encryption system. The results show that FPHYBCM-PRBG is suitable for image encryption based on stream cipher and outperform some encryption algorithms in sufficient way to enhance the security and robust against brute force attack with low maximum frequency and throughput.