Design of Low Power C-Element Based Dual Data Rate Flip-Flip

Fulfillment of dual edge flip-flops gets freshly develops into the goal of countless exploration to sustain expressive accomplishment of digital schemes while compressing power expenditure. Powerful low-power flip-flops acquire absolute basic district elements Gross sudden width of histrionic organizes successive circumferences / circuits. Conclude individually and remarkable testing as long as their vulnerability, Q-Delay, Rise Time Path, Fall Time Path and Average Power Consumption. While Power reveals smart effective count regarding the latest electrifying circuit transistors, uncertainly we survive balancing, including scheming comic numbers such as transistors that suspense each number of flip-flops. Analysis / inquiry on static / stable circuits is performed by Dual Data Rate (DDR) using PTM CMOS-16 nm technology alongside 5MHZ frequencies, including their victory procedure. Sensational Dual Data Rate (DDR) Flip-Flop uses 30% less capacity / power, including 14% lower C-Q delay. This paper's proposed architecture is to analyze logic size, area, and power consumption using tanner tool.