stnolting/neorv32: v1.5.8

This list shows the main core changes since the last release. See the project's changelog for more information.

• fixed bug in custom functions subsystem CFS: address map layout overlapping
• fixed minor bug in FIFO component (setups with FIFO_DEPTH = 1 caused mapping issues)

• added RISC-V Zmmul ISA extension (subset of M extension: integer HW multiplier, but no HW divider; intended for area-constrained setups)
• bootloader is more independent of HW configuration (no need for UART, MTIME, GPIO anymore); added several options to customize default bootloader
• :warning: removed top's fast IRQ (FIRQ) inputs soc_firq_i
• :warning: removed numerically-controller oscillator module (NCO)
• added new processor module stream link interface (SLINK) providing up to 8 independent RX and TX links
• increased GPIO port size from 32-bit to 64-bit
• added new processor module external interrupt controller (XIRQ) providing up to 32 processor-external interrupt request lines
• new performance-vs-ares configuration generic: CPU_IPB_ENTRIES defines size of CPU's instruction prefetch buffer
• reworked NEOLED module: IRQ now uses fifo half-full fill level; added option to send LED RESET command as explicit FIFO command
• (re-)added mstatush CSR (hardwired to zero)
• minor logic optimizations to reduce area requirements and switching activity and to shorten critical path

Merged pull requests:

• #89 Make uart_rx a verification component
• #90 Make uart_rx a VUnit verification component. Step 4.
• #92 sim: update readme
• #93 [setups/vivado] arty-a7-test-setup: define multiple filesets, set board, set language
• #95 Add loopback test for SLINK
• #98 OrangeCrab
• #99 osflow rework
• #100 [docs] move Makefile from project root to subdir 'docs'
• #104 [setups/osflow] cleanup
• #107 [setups/osflow] update OrangeCrab constraints file
• #109 riscv-arch-test script cleanup
• #114 use RISCV_PREFIX instead of RISCV_TOOLCHAIN
• #116 [ci] add workflow 'Containers'
• #117 mv riscv-arch-test sw/sig-arch-test
• #118 [sw/example] add common.mk
• #119 [riscv-arch-test] measure execution time of each test
• #120 [sim/ghdl] use --workdir=build
• #123 [docs] update references to isa-test
• #124 Split ISA test suites in multiple jobs and rework makefiles
• #125 Fix source/sink mixup in SLINK docs
• #127 [ci/windows] fix RISCV_PREFIX

Closed issues:

• #77 Use ProcessorTop templates in non osflow examples
• #97 Having trouble building the iCESugar example
• #106 Constraints file for OrangeCrab r0.2
• #108 question: Is the prebuilt build support rv32IMAC ISA extension or just rv32imc?
• #122 Add halfway interrupts for SLINK interface