Implementing VexRiscv Based Murax SoC on Arty A7 Artix-7 PCB from Digilent and Enabling JTAG Connection through Xilinx's BSCANE2 Debug IP

Up-to-date FPGA evaluation boards, like the Digilent Arty A7 mounting a Xilinx Artix-7 FPGA, come with an integrated
FTDI chip which makes programming and debugging quite easy. In our work, we synthesized the VexRiscv based Murax
processor to an Artix-7 FPGA and at first lead out the JTAG relevant signals of the Riscv core to the board’s Pmod
Header to connect to a dedicated Olimex JTAG Adapter through a second USB cable. As it turns out, this extra effort
on hardware can be minimized by use of some Xilinx Debug IP named BSCANE2. Collecting the required information on how
to do this was tedious. So we came to the decision to document our path to success with this short report. We expect
that the reader is familiar with the README.md to be found at https://github.com/SpinalHDL/VexRiscv and that the
reader is capable of generating the Murax SoC as it is described there.