Best Practice Guide Intel Xeon Phi v2.0
Creators
- 1. LRZ, Germany
- 2. IICT-BAS, Bulgaria
- 3. KTH, Sweden
- 4. CSC, Finland
- 5. SURFsara, Netherlands
- 6. NCSA, Bulgaria
- 7. IT4Innovations, Czech Republic
- 8. BSC, Spain
- 9. University of Oslo, Norway
Description
This Best Practice Guide provides information about Intel’s Many Integrated Core (MIC) architecture and programming
models for the first generation Intel® Xeon Phi™ coprocessor named Knights Corner (KNC) in order
to enable programmers to achieve good performance out of their applications.
The guide covers a wide range of topics from the description of the hardware of the Intel® Xeon Phi™ coprocessor
through information about the basic programming models as well as information about porting programs up to
tools and strategies how to analyse and improve the performance of applications. Through the highly parallel architecture
and the use of high bandwidth memory, the MIC architecture allows higher performance than traditional
CPUs for many types of scientific applications. The guide was created based on the PRACE-3IP Intel® Xeon
Phi™ Best Practice Guide. New is the inclusion of information about applications, benchmarks and European
Intel® Xeon Phi™ based systems.
Files
Best-Practice-Guide_Intel-Xeon-Phi.pdf
Files
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