Design of High-Speed Hybrid Carry Select Adders using VHDL
Creators
- 1. G. H. Raisoni Academy of Engineering and Technology, Nagpur
Description
Carry select adder (CSA) is a square-root time high-speed adder. CSA is one of the fastest adders used in many data processing systems to perform fast arithmetic operations. In this project we propose to design hybrid carry select adders with a focus on high speed. CSA is a compromise between the longer delay Ripple carry adder (RCA) and the shorter delay Carry look-ahead adder (CLA). Conventionally carry select adders are realize using the full adders and 2:1 multiplexers. On the other hand hybrid carry select adders involve a combination of carry select and carry look-ahead adders.In this work, we propose to design hybrid carry select adders involving carry select and carry look-ahead adders with and without ripple carry adder (RCA) using very high speed integrated circuits hardware description language (VHDL).
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Additional details
References
- V. Kokilavani, K. Preethi,and P. Balasubramanian, “FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders” Hindawi Publishing Corporation Advances in Electronics Volume 2015, Article ID 713843.
- Basant Kumar Mohanty, Senior Member, IEEE, and Sujit Kumar Patel, “Area– Delay–Power Efficient Carry-Select Adder” IEEE Transaction on circuits and systems— II: express briefs , vol .61, no.6, Jun 2014.
- Shivani Parmar, Kirat Pal Singh, “Design of high speed hybrid carry select adder,” IEEE Transactions on VLSI Systems, 978-1-4673-4529-3/12 -2012.
- K. Preethi,and P. Balasubramanian, “FPGA Implementation of Synchronous section-carry base carry look-ahead adder” 2nd International conference on devices, circuits and systems (ICDCS), 2014 IEEE
- Shamim Akhter, Saurabh Chaturvedi, Kilari Pardhasardi, “CMOS implementation of efficient 16 bit square root carry select adder” 2nd International Conference on Signal Processing and Integrated Networks (SPIN), 2015 IEEE
- J.Monteiro, J. L. G¨untzel, and L. Agostini, “A1CSA: an energyefficient fast adder architecture for cell-based VLSI design,” in Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 11), pp. 442–445, Beirut, Lebanon, December 2011.