30nm DG-FinFET 3D Construction Impact Towards Short Channel Effects

This paper presents an investigation on properties of Double Gate FinFET (DG-FinFET) and impact of physical properties of FinFET towards short channel effects (SCEs) for 30 nm device, for which the depletion-layer widths of the source-drain relates to the channel length aside from constant fin height (HFIN) and the fin thickness (TFIN). Virtual fabrication process of 3- dimensional (3D) design is applied throughout the analysis. Further to that, its electrical characterization is employed and the ratio of drive current against the leakage current (ION/IOFF ratio) of the FinFET design on the other hand has showcased substantial difference at 563138.35 compared to the prediction made by the International Technology Roadmap Semiconductor (ITRS) 2013. Conclusively, the incremental in ratio has fulfilled the anticipated increment on the drive current (ION) as well as reductions of the leakage current (IOFF). Threshold voltage (VTH) meanwhile has also achieved the nominal prediction that is obliged by the International Technology Roadmap Semiconductor (ITRS) 2013 for which is at 0.676±12.7% V. The ION, IOFF and VTH obtained from the device has evidently met the minimum condition by ITRS 2013 for low power Multi-Gate technology.