Accurate leakage current models for MOSFET nanoscale devices

This paper underlines a closed form of MOSFET transistor’s leakage current mechanisms in the sub 100nmparadigm.The incorporation of drain induced barrier lowering (DIBL), Gate Induced Drain Lowering (GIDL) and body effect (m) on the sub-threshold leakage (Isub) was investigated in detail. The Band-To-Band Tunneling (IBTBT) due to the source and Drain PN reverse junction were also modeled with a close and accurate model using a rectangular approximation method (RJA). The three types of gate leakage (IG) were also modeled and analyzed for parasitic (IGO), inversion channel (IGC), and gate substrate (IGB). In addition, the leakage resources due to the aggressive reduction in the oxide thickness (<5nm) have been investigated. Simulation results using HSPICE exhibits a tremendous agreement with the BSIM4 model. The dominant value of the sub-threshold leakage was due to the DIBL and GIDL effects. Various recommendations regarding minimizing the leakage current at both device level and the circuit level were suggested at the end of this paper.