Area and power efficient VLSI architecture of mode decision in integer motion estimation for HEVC video coding standard

In this paper, we propose a new parallel hardware architecture for the mode decision algorithm, that it is based on the Sum Absolute of the Difference (SAD) for compute the motion estimation, which is the most critical algorithm in the recent video encoding standard HEVC. In fact, this standard introduced new large variable block size of the motion estimation algorithm and therefore the SAD require a more reduced execution time in order to achieve the real time processing even for the ultra-high resolution sequences. The proposed accelerator executes the SAD algorithm in a parallel way for all sub-block prediction units (PUs) and coding unit (CU) whatever their sizes, which turns in a huge improvements in the performances, given that all the block sizes, PUs in each CU, are supported and processed in the same time. The Xilinx Artix-7 (Zynq-7000) FPGA is used for the prototyping and the synthesis of the proposed accelerator. The mode decision for the motion estimation scheme is implemented with 32K LUTs, 50K registers and 108Kb BRAMs. The implementation results show that our hardware architecture can achieve 30 frames per second of the 4K (3840×2160) resolutions in real time processing at 115.15MHz.