Experimental Data (Including Hardware Variants) Measuring Runtime for Trace Assisted Caching

As part of the Thesis "Using Tracing to Enhance Data Cache Performance in CPUs" experiments were conducted to measure the runtime of different benchmarks running on a CPU configured with different varieties of cache. The five variants encompassed a processor with no cache, an 8-way Set-Associative Cache, a Direct-Mapped Cache and then a new Trace Assisted Cache in both Direct-Mapped and Set Associative variants. 

The intent was to measure whether adding the Trace Assistance to the cache would significantly reduce runtime. The files contained in this submission include all the files that were generated during the experiments as well as the final dataset this produced. Included in the *.tar.xz file is a set of directories organised into folders for each combination of benchmark and hardware variant. Each folder is labelled <<benchmark>>_<<variant_key>> so fac_nc means the fac benchmark run on the hardware that had No Cache. Any hardware variant that begins cc stands for complex cache and refers to the Trace Assisted Versions.

Inside these folders are contained the compiled executables and linker files that were used, all of the code generated by the automation framework, the Vivado project that was created to enable the hardware to be synthesised, any bitfiles generated by this process and the resulting vcd files from which the data in the XLS file was extracted. Vivado 2018.2 was used to create the bitfiles and so that version or higher would be required to open the files. Also as a warning, when expanded the experiments archive is over 100GB in size so please be aware of this when downloading.

The XLSX file contains the measured results, split by benchmark and hardware and is provided as a summary of the vast quantities of data included in the archive.