Implementation and Design of FIR Filters using Verilog HDL and FPGA

Digital filters play a major role in Very Large-Scale Integration Technology (VLSI), as most VLSI systems use addition as an integral operation. One such filter is FIR filter, whose basic implementation is achieved by adders. This paper mainly aims at designing a Moving Average 4-tap FIR filter using Verilog HDL and is implemented using Xilinx software and Spartan 6 FPGA kit with the concepts of Multiply and Accumulate (MAC) operation and convolution.